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异步fifo要是接入的读写时钟相同 ,这种设计会出错吗
ExASIC1
asked May 27
0 1 49
design
用synplify做fpga综合,然后把综合后的.vm文件做vcs仿真,端口全是高阻。有人遇到过吗
ExASIC1
asked May 27
0 0 6
verification
集成内部ip的parameter仿真时候如何在环境中改掉
ExASIC1
asked May 27
0 1 27
design
什么是存内计算?
ExASIC1
asked May 27
0 0 23
design
有什么办法可以在SOC里 抓出某一个register的path
ExASIC1
asked May 27
0 1 29
design
VCS仿真可以用simprofile分析耗时,xrun用哪个开关呢
ExASIC1
asked May 27
0 1 8
verification
怎么用两个1k深度sp sram,搭一个1k深度的双口sram呢
ExASIC1
asked May 27
0 3 17
design
verilog function里面加了automatic,Verdi还是看不了波形?
ExASIC1
asked May 27
0 1 14
verdi
跑 post PT 报这个error: Current design is not in min-max mode. (DES-013)
ExASIC1
asked May 27
0 0 3
sta
请教个问题为啥子axi总线读通道是2个,为啥不是像写通道搞3个?
ExASIC1
asked May 27
0 1 19
design
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