（1）
reg out;
always@(posedge clk)
begin
if (enb)
out <= #1 in;
end
（2）
reg out;
always@(posedge clk)
begin
if (enb)
out <= #1 in;
else
out <= #1 out;
end
两种Verilog写法综合结果是一样的吗？
Viewed 116
（1）
reg out;
always@(posedge clk)
begin
if (enb)
out <= #1 in;
end
（2）
reg out;
always@(posedge clk)
begin
if (enb)
out <= #1 in;
else
out <= #1 out;
end