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formality做比较的时候,网表上的value=x啥意思?
ExASIC13
asked Dec 30, 2022
0 0 23
formal
触发器的Q端输出作为时钟,怎么约束
ExASIC13
asked Dec 30, 2022
0 1 42
sta synthesis
dc中使用get_cell *获得所有的cell,但是在dc的batch界面中只打印了部分的cell,其他的用...代替了
ExASIC13
asked Dec 30, 2022
0 1 24
synthesis
我想看下整体的soc环境是咋样搭建的
ExASIC13
asked Dec 30, 2022
0 0 50
soc verification
在run phase的raise object前增加延时可以推迟driver启动吗
ExASIC13
asked Dec 15, 2022
0 0 16
uvm verification
SDF Warning: $setup/hold不支持负值?
ExASIC13
asked Dec 15, 2022
0 0 28
postsim verification
APR里怎么给floating input pin加tie cell?试过addTieHiLo和attach,会报错
ExASIC13
asked Dec 15, 2022
0 0 27
backend
DC里怎么看一个port的方向?
ExASIC13
asked Dec 15, 2022
0 0 16
synthesis
parameter与define不同使用场景
jillian1
asked Dec 13, 2022
0 1 51
verification
请教大佬们一个问题,数据帧格式,这个帧头和帧尾有啥讲究吗
ExASIC13
asked Dec 13, 2022
0 0 24
design
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