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IC技术圈问答
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组合逻辑if else和assign,哪个写法综合的门电路比较多
ExASIC
1
asked Apr 17
0
2
48
design
python怎么做verilog宏替换和展开
ExASIC
1
asked Apr 15
0
3
53
python
script
python怎能删除verilog文件中的多行注释
ExASIC
1
asked Apr 15
0
1
44
python
script
SOC中IOMUX模块怎么用脚本生成
ExASIC
1
asked Apr 15
0
0
14
design
script
tcl里出现600.19999999998?
ExASIC
1
asked Apr 15
0
1
49
script
kdb has been updated by other process问题
ExASIC
1
asked Apr 15
0
0
58
verification
verdi
什么是systemrdl?
ExASIC
1
asked Apr 15
0
2
24
design
verification
verilog代码a=b[cnt*5+5:cnt*5]编译报错
ExASIC
1
asked Apr 15
0
0
17
design
什么是堆,什么是栈
ExASIC
1
asked Apr 15
0
1
36
design
怎么防止rm误删重要文件?
ExASIC
1
asked Apr 15
0
0
14
linux
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