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IC技术圈问答
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怎么看sdf文件的版本
ExASIC
1
asked Apr 15
0
0
18
backend
verification
什么叫过采样?
ExASIC
1
asked Apr 15
0
0
11
design
组合逻辑综合出来的毛刺,是不是加约束毛刺就可以消失
ExASIC
1
asked Apr 15
0
1
41
synthesis
什么是PSS
ExASIC
1
asked Apr 15
0
0
8
verification
5000字!FPGA开发必须知道的五件事
苏格不拉底
1
asked Apr 11
0
1
58
fpga
spyglass 使用问题 STARC05-1.4.3.4
dongdong
1
asked Apr 3
0
0
153
spyglass
sv dpi-c的c代码中,vcs不能识别FILE类型文件
ExASIC
1
asked Apr 3
0
0
35
dpi-c
systemverilog
verification
sv中多个case并行跑仿真,往同一个文件中写仿真结果,如何lock文件防止冲突?
ExASIC
1
asked Apr 3
0
2
52
systemverilog
verification
sv的tb中如何在时钟周期(a,b)的范围内产生随机时钟
ExASIC
1
asked Mar 31
0
1
68
verification
xrun混仿verilog和vhdl时fsdb里没有vhdl的波形?
ExASIC
1
asked Mar 31
0
1
24
verification
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