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IC技术圈问答
Questions
Tags
design
前端设计
31 Questions
异步fifo要是接入的读写时钟相同 ,这种设计会出错吗
ExASIC
1
•
asked May 27
0
1
49
design
集成内部ip的parameter仿真时候如何在环境中改掉
ExASIC
1
•
asked May 27
0
1
27
design
什么是存内计算?
ExASIC
1
•
asked May 27
0
0
23
design
有什么办法可以在SOC里 抓出某一个register的path
ExASIC
1
•
asked May 27
0
1
29
design
怎么用两个1k深度sp sram,搭一个1k深度的双口sram呢
ExASIC
1
•
asked May 27
0
3
17
design
请教个问题为啥子axi总线读通道是2个,为啥不是像写通道搞3个?
ExASIC
1
•
asked May 27
0
1
19
design
有人了解sg2042的核是用的算能自研的微结构么
ExASIC
1
•
asked May 6
0
0
10
design
matlab算法移植到FPGA有什么好的方法
ExASIC
1
•
asked May 6
0
1
63
算法
design
DFF的reset和set哪个优先级高
ExASIC
1
•
asked May 6
0
0
12
design
用sv做设计的公司多吗
ExASIC
1
•
asked Apr 19
0
0
16
systemverilog
design
1
(current)
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