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IC技术圈问答
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design
前端设计
31 Questions
a <= 1'b0,a是一个多位宽寄存器,复位时a的所有 bit会全部变0吗?
ExASIC
1
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asked Apr 17
0
4
42
design
组合逻辑if else和assign,哪个写法综合的门电路比较多
ExASIC
1
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asked Apr 17
0
2
48
design
SOC中IOMUX模块怎么用脚本生成
ExASIC
1
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asked Apr 15
0
0
14
design
script
什么是systemrdl?
ExASIC
1
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asked Apr 15
0
2
24
design
verification
verilog代码a=b[cnt*5+5:cnt*5]编译报错
ExASIC
1
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asked Apr 15
0
0
17
design
什么是堆,什么是栈
ExASIC
1
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asked Apr 15
0
1
36
design
什么叫过采样?
ExASIC
1
•
asked Apr 15
0
0
11
design
有没有哪家公司把多个module写在同一个文件中,请问这是什么用意?
ExASIC
1
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asked Mar 21
0
4
204
design
软件是如何控制硬件的?
ExASIC
1
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asked Mar 18
0
1
80
design
有没有CCIX协议的中文版
ExASIC
1
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asked Mar 16
0
1
62
design
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