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IC技术圈问答
Questions
Tags
design
前端设计
31 Questions
在fifo的输入输出位数不一致的情况下,可以修改数据的顺序的吗?
ExASIC
1
•
asked Mar 11
0
2
40
design
为什么dff有时候采时钟沿之前,有时候采之后?
ExASIC
1
•
asked Feb 15
0
2
89
design
可以对reg信号assign吗?
ExASIC
1
•
asked Feb 14
0
1
70
design
verification
verilog中的case到底是并行的还是串行的,有优先级吗?
ExASIC
1
•
asked Feb 13
0
1
63
design
请问riscv f对于非规格化数是怎么支持的
ExASIC
1
•
asked Dec 30, 2022
0
0
36
riscv
design
请教大佬们一个问题,数据帧格式,这个帧头和帧尾有啥讲究吗
ExASIC
1
•
asked Dec 13, 2022
0
1
59
design
有哪些方法可以降低功耗?
ExASIC
1
•
asked Dec 8, 2022
0
1
113
lowpower
backend
design
post mask eco时,为什么conformal还会删cell啊,这不就动到了base layer了吗?
ExASIC
1
•
asked Nov 28, 2022
0
0
65
eco
design
车规芯片设计或者验证,有没有书籍?
ExASIC
1
•
asked Nov 26, 2022
0
0
62
iso26262
design
verification
PT静态时序分析时fix_eco_timing怎么设置可自动修复时钟源直接扇出到输出的时序违例呢?
ExASIC
1
•
asked Nov 21, 2022
0
0
27
sta
eco
design
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