IC技术圈问答
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sta
静态时序分析
10 Questions
为什么有了STA还需要做后仿
ExASIC
33
•
asked Sep 25
0
1
64
postsim
sta
verification
跑 post PT 报这个error: Current design is not in min-max mode. (DES-013)
ExASIC
33
•
asked May 27
0
0
28
sta
如何从波形中查看建立时间保持时间
zj515018
1
•
asked May 25
0
1
79
dc
verilog
sta
i2c综合后大家怎么做scl和sda的data2data check
ExASIC
33
•
asked Mar 8
0
1
64
sta
synthesis
如何约束ANA到DIG上面的这条线的timing呢
ExASIC
33
•
asked Feb 26
0
1
80
sta
触发器的Q端输出作为时钟,怎么约束
ExASIC
33
•
asked Dec 30, 2022
0
1
105
sta
synthesis
请问下,PT怎么样可以显示出来clock source latency?
ExASIC
33
•
asked Nov 30, 2022
0
0
88
sta
在pt里面怎么查看内部时钟树到某个output pin的时序报告?
ExASIC
33
•
asked Nov 30, 2022
0
0
18
sta
请教一下,PT工具里面如何报出各种VT的比例?
ExASIC
33
•
asked Nov 24, 2022
0
1
62
backend
sta
PT静态时序分析时fix_eco_timing怎么设置可自动修复时钟源直接扇出到输出的时序违例呢?
ExASIC
33
•
asked Nov 21, 2022
0
0
113
sta
eco
design
1
(current)