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静态时序分析

9 Questions
跑 post PT 报这个error: Current design is not in min-max mode. (DES-013)
ExASIC1
• asked May 27
0 0 3
sta
如何从波形中查看建立时间保持时间
zj5150181
• asked May 25
0 1 19
dc verilog sta
i2c综合后大家怎么做scl和sda的data2data check
ExASIC1
• asked Mar 8
0 1 48
sta synthesis
如何约束ANA到DIG上面的这条线的timing呢
ExASIC1
• asked Feb 26
0 1 63
sta
触发器的Q端输出作为时钟,怎么约束
ExASIC1
• asked Dec 30, 2022
0 1 77
sta synthesis
请问下,PT怎么样可以显示出来clock source latency?
ExASIC1
• asked Nov 30, 2022
0 0 59
sta
在pt里面怎么查看内部时钟树到某个output pin的时序报告?
ExASIC1
• asked Nov 30, 2022
0 0 8
sta
请教一下,PT工具里面如何报出各种VT的比例?
ExASIC1
• asked Nov 24, 2022
0 1 28
backend sta
PT静态时序分析时fix_eco_timing怎么设置可自动修复时钟源直接扇出到输出的时序违例呢?
ExASIC1
• asked Nov 21, 2022
0 0 27
sta eco design
  • 1 (current)

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