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synthesis

综合

28 Questions
synplify+vivado 联合使用,vivado实现时报错
liqunxiong1
• asked Nov 23
0 0 9
布局布线 synplify vivado fpga synthesis
dc、pt里如何查看db文件对应的condition名字?
ExASIC33
• asked Nov 16
0 0 16
pt synthesis
dc里get_cells打印不全,有省略号怎么办
ExASIC33
• asked Oct 17
0 1 22
synthesis
代码里有3个寄存器是不同的门控条件,综合结果有可能会把3个条件相或,生成一个公共的门控时钟吗?
ExASIC33
• asked Oct 13
0 0 13
lec design synthesis
dc里get_ports怎样筛选出xxx开头的输入port?
ExASIC33
• asked Sep 8
0 1 23
synthesis
apb能工作在512MHz吗
ExASIC33
• asked Aug 5
0 1 102
synthesis
set_clock_gating_style这个不知道该怎么设定,求助
ExASIC33
• asked Aug 1
0 0 56
synthesis
dc里面怎么把一个pin接到1'b0上去?
ExASIC33
• asked Jul 31
0 0 34
eco synthesis
怎么把lib转成db
ExASIC33
• asked Apr 21
0 1 90
synthesis
组合逻辑综合出来的毛刺,是不是加约束毛刺就可以消失
ExASIC33
• asked Apr 15
0 1 64
synthesis
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