IC问答

Questions Tags

synthesis

综合

13 Questions
代码a=b&~b综合出来的电路是啥样的啊
ExASIC13
• asked Jan 17
0 2 26
synthesis
一般走dcg flow,到innovus中该怎么处理呢
ExASIC13
• asked Jan 17
0 0 11
backend synthesis
有了综合面积,怎么估APR面积?
ExASIC13
• asked Jan 17
0 3 15
backend synthesis
genus怎么移除掉空模块
ExASIC13
• asked Jan 17
0 1 6
genus synthesis
触发器的Q端输出作为时钟,怎么约束
ExASIC13
• asked Dec 30, 2022
0 1 41
sta synthesis
dc中使用get_cell *获得所有的cell,但是在dc的batch界面中只打印了部分的cell,其他的用...代替了
ExASIC13
• asked Dec 30, 2022
0 1 24
synthesis
DC里怎么看一个port的方向?
ExASIC13
• asked Dec 15, 2022
0 0 16
synthesis
dc里面打开组合逻辑环的check需要设置啥啊
ExASIC13
• asked Nov 30, 2022
0 0 14
synthesis
有什么办法可以对rtl加密还能进行综合?
ExASIC13
• asked Nov 28, 2022
0 0 31
synthesis verification
有没有人知道dc的GTECH库和工艺库有什么区别?
ExASIC13
• asked Nov 27, 2022
0 1 43
synthesis
  • 1 (current)
  • 2
  • NextNext

Built on Answer - the open-source software that powers Q&A communities.
Made with love © 2023 IC问答.