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IC技术圈问答
Questions
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verification
验证
61 Questions
为什么verdi看有的模块状态机就能显示字符串,有的模块只能显示值吗
ExASIC
1
•
asked Mar 11
0
1
62
verification
verdi
force可以把一个信号force成另一个信号不
ExASIC
1
•
asked Mar 11
0
1
42
verification
vcs仿真时卡在0时间,怎么debug?
ExASIC
1
•
asked Mar 11
0
2
57
verification
vcs有单独针对某个模块或者单元定义nospecify的命令吗
ExASIC
1
•
asked Mar 8
0
1
33
vcs
verification
simvision中,case的类中定义的参数可以直接dump下来吗?
ExASIC
1
•
asked Mar 8
0
1
16
verification
synopsys hvplan怎么用
ExASIC
1
•
asked Feb 26
0
1
61
verification
verdi
一亿门的网表后仿怎么加速?
ExASIC
1
•
asked Feb 19
0
2
74
postsim
verification
后仿仿不过,都有哪方面的原因?
ExASIC
1
•
asked Feb 19
0
1
65
postsim
verification
可以对reg信号assign吗?
ExASIC
1
•
asked Feb 14
0
1
70
design
verification
vcs里哪个参数可以自动给所有的时序逻辑加0.1ns延时?
ExASIC
1
•
asked Feb 7
0
1
59
vcs
verification
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